Home » Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Brandon Noia

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Brandon Noia

Published November 19th 2013
ISBN :
Kindle Edition
274 pages
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 About the Book 

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing andMoreThis book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.